Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits

In order to ensure a high product quality some authors propose pseudo-exhaustive or verification testing. This is applicable if each primary output of the combinational circuit only depends on a small set of primary inputs, where all possible patterns can be enumerated completely. But in CMOS-circuits even a single stuck-open fault may fail to be detected this way, and the already proposed additional test of each input transition is not sufficient either. In this paper a method based on linear feedback shift registers over finite fields is presented to generate for a natural number n a pattern sequence with minimal length detecting each m-multiple stuck-open fault for m ≤ n. A hardware architecture is discussed generating this sequence, and for n = 1 a built-in self-test approach is presented detecting all combinations of multiple combinational and single stuck-open faults.